| 摘要 |
PURPOSE:To use a test mode function for a semiconductor element which has no unnecessary terminal by providing a test signal generating circuit which generates a test signal for controlling the test mode function according to the combination of applied external input signals. CONSTITUTION:A test signal generating circuit consists of a NAND circuit 1, a NOR circuit 2, a delay circuit 3, an AND circuit 4, and a latch circuit 5 and a test clock signal TC as a test signal which is set once is latched so that it does not become unstable until resetting. Further, internal signals phi1 and phi2 are generated with the inverse of external input signals RAS and CAS and a read/write signal R/W. Then, the test signal generating circuit sets the signal R/W to 'L' during a period wherein the inverse of the signal RAS is at 'H' and the inverse of the signal CAS is at 'H', and the level of the test clock TC is set with the value ('H' or 'L') of the current data input signal DIN, thereby controlling the start and stop of a test mode. |
