| 摘要 |
PURPOSE:To decrease aligning exposure processes to twice, by performing the formations of the gate electrode of each channel MOS transistor and source and drain regions by the same aligning exposure process. CONSTITUTION:A polycrystalline silicon layer 5 is etched by using first and second masks 6A and 6B. A gate electrode 7A of an N-channel MOS transistor 10 is formed. Then, impurities are implanted by an ion implantation method by using the electrode 7A and the mask 6A. N-type source and drain regions 8 of the transistor 10 are formed. The polycrystalline silicon layer 5 is etched by using third and fourth masks 6C and 6D, and a gate electrode 7B of a P- channel MOS transistor 20 is formed. Impurities are introduced by ion implantation method using the electrode 7B and the mask 6C, and P-type source and drain regions 9 of the transistor 20 are formed. Thus the aligning exposure processes can be reduced to twice. |
