| 摘要 |
<p>A programmable FIFO buffer is disclosed which including a (serial) input register for receiving signals representing in serial format a word of data and for developing signals representing the data word converted to parallel format, a control register for controlling the serial-to-parallel conversion process, a (parallel-input parallel-output-type) FIFO buffer for storing the data word, a (serial) output register for receiving from the buffer, signals representing in parallel format a word of data stored in the buffer and for developing signals representing the stored data word converted to serial format, and another control register for controlling the parallel-to-serial conversion process.</p> |
