| 摘要 |
<p>A BIMOS circuit is provided wherein an output terminal 14 is coupled between an upper NPN and a lower PNP pair of push-pull transistors 11, 12 for providing high current drive capability along with no d.c. power dissipation. A P-channel MOS transistor 16 is coupled between a node 17 and both the collector of the NPN transistor and a first supply voltage terminal for biasing the NPN transistor. An N-channel MOS transistor 18 is coupled between the node and both the collector of the PNP transistor and a second supply voltage terminal for biasing the PNP transistor. The gates of the MOS devices are connected to an input terminal 21. The node is further coupled to the bases of the NPN and PNP transistors and is coupled to the output terminal by a transmission gate 19 or a resistor 22 for increasing the output voltage swing.</p> |
