| 摘要 |
The subject of the invention is an adder circuit in 51111 code, which consists of 36 individual non-dual adder circuits (5), and has a dual full adder (3) as a supplementary circuit to process the value 5. This adder circuit is also provided with a partial sum derivation circuit (6), which then derives a partial sum with the numeric value 5 from the sum or remaining sum of the main circuit (1) if this sum is greater than the number 4. <IMAGE>
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