| 摘要 |
PURPOSE:To perform error correction and to improve the transmission efficiency by dividing the reception signal of one frame by a checking polynomial and regarding the position, where the remainder is 0, as a frame synchronizing position to perform synchronization detection. CONSTITUTION:An operating circuit 1 which divides a reception signal F(x) of one frame by a checking polynomial G(x) and a frame counter 2 are provided. Unless a syndrome S(x) obtained by the operating circuit 1 is 0, the frame counter 2 is counted up more than by a reception clock signal, and error bits are corrected in an error correcting part 3 on a basis of the syndrome S(x). If the syndrome S(x) is 0, the frame counter 2 is counted up by only the reception clock signal because of the frame synchronizing position and is so synchronized that the syndrome S(x) is 0. Even if no frame synchronizing bits are included, the operating circuit 1 for error correction is used to detect frames synchronously, and the circuit constitution is simplified and the transmission efficiency is improved. |
