| 摘要 |
PURPOSE:To ensure the highly effective multiplex application of time by using plural pieces of a unit signal precessing circuit consisting of an arithmetic processing circuit, a temporary memory circuit and a control circuit for these processing and memory circuits. CONSTITUTION:Input data read into a latch L6 in a 1st step and at the same time 1st coefficient CI is fetched to a latch L5 from a coefficient memory 7. In a 2nd step, the result of multiplication of said input data and the coefficient CI is fetched by two letches L8 and L10. While the data to be added with those results of both latches L8 and L10 are fetched to the latches L7 and L9 from a delay memory 6. In a 3rd step, the next result of multiplication is fetched by latches L8 and L10 and at the same time the result of addition obtained by an arithmetic circuit 4 between both latches L7 and L8 is fetched by a register R13 with the result of addition of both latches L9 and L10 fetched by a memory Z1 respectively. In such a way, a pipeline processing method is applied to carry out the multiplication processing of the present data simultaneously with the addition processing of the preceding data. Furthermore, two adders 4 work in parallel with each other. |
