| 摘要 |
PURPOSE:To reduce the dispersion of erasing characteristics, and to minimize the stepped disconnection of a wiring formed to a surface layer section by shaping a diffusion region for an erasing gate electrode into a base body and forming only a floating gate electrode conductor layer and a control gate electrode conductor layer onto the base body. CONSTITUTION:Control gate electrodes 20 are shaped in common with floating gate electrodes 18 for a plurality of memory cells (surrounded by a broken line) disposed in the lateral direction, a field insulating film 11 is removed partially in an element isolation region 12 to expose a substrate 10, and an erasing gate electrode 21 consisting of an N-type diffusion region is formed to the exposed substrate. The erasing gate electrode 21 is shared at every two memory cell arranged in the longitudinal direction, and one parts of the electrode 21 are overlapped each other with the floating gate electrodes 18 through a gate insulating film 22. Accordingly, the dispersion of erasing characteristics is improved. |
