| 摘要 |
PURPOSE:To shorten a process, to reduce the stepped disconnection of a wiring formed to a surface layer section and to equalize erasing characteristics by shaping an erasing gate electrode and a control gate electrode by patterning the conductor layer of the same layer. CONSTITUTION:A floating gate electrode 18 by patterning a first layer polycrystalline silicon layer is formed onto a gate insulating film 17 shaped onto the surface of a substrate 10 in a channel region 16, a gate insulating film 19 is formed onto the surface of the gate electrode 18, and a control gate electrode 20 and an erasing gate electrode 21 by patterning a second layer polycrystalline silicon layer are each shaped onto the gate insulating film 19. Accordingly, processes can be shortened, the generation of displacement on positioning is reduced because the erasing gate electrode 21 can be formed in a self-alignment manner to the floating gate electrode 18, erasing characteristics can be equalized, the surface is flattened, and the generation of the stepped disconnection of metallic wirings 22, 24 shaped to a surface layer section can be prevented. |
