High performance output driver

摘要

A memory, which has an amplifying circuit which provides a pair of differential signals representative of data contained in a memory cell selected by an address, has an output driver which receives this pair of differential signals on a pair of input lines. The output driver is tri-stated in response to an address transition so that the output driver provides only either valid data or a high impedance. The data provided by the differential signals is latched on the input lines by data latches after a predetermined time delay if new valid data has not appeared. The data latches used add less capacitance to the pair of input lines than those used previously.