| 摘要 |
PURPOSE:To improve the degree of integration of a semiconductor integrated circuit device by a method wherein an Si selective epitaxial growing method and an RIE etching method of CVD SiO2 are used. CONSTITUTION:An N-WELL 32 in a P-MOS region is formed on a P-type Si substrate 31, and P<-> type epitaxial Si layer 34 is formed by patterning the resist on a deposited CVD SiO2 film 33 using photoetching method and by performing etching using RIE. Then, a nitride film layer 35 is formed by thermal ly nitriding the surface of the Si layer 34 in a high frequency plasmic atmo sphere, and a CVD SiO2 film 36 is formed. Subsequently, when overall etching is performed on the CVD SiO2 film 36 using RIE, the SiO2 film is left on the side wall of the P<-> epitaxial Si layer 34, and besides, when the second P<-> epitaxial Si film 37 is formed, the SiO2 film is left on the side wall of the Si layer 34 is formed into the SiO2 layer 38 to be used for isolation of an element. Then, an N<-> WELL 39 is formed on the side of PMOS by performing the photoetching method for the N<-> WELL and a phosphorus implantation, a gate oxide film 40 is formed, and a POLLY Si gate electrode 41 is formed.
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