发明名称 BI-CMOS INTEGRATED CIRCUIT
摘要 PURPOSE:To make a bipolar transistor operable at high speed by a method wherein the fourth buried layer with the same conductivity as that of a substrate is formed in the first buried layer; the opposite conductivity type thin epitaxial layer is formed in the first-fourth buried layers and an isolation buried layer; and a well region is formed in contact with the fourth buried layer and the isolation buried layer. CONSTITUTION:The first N type buried layer 2 with relatively higher resistance and deeper junction and the second N type buried layer 3 with lower resistance and shallower junction than those of the first layer 2 are formed in a P type substrate 1 next P type buried layers 4 are formed in the buried layer 2 and a bipolar element isolation region. Furthermore, after growing an N type epitaxial layer 5, a P type well layer 6 is formed to form a well region of an N channel type MOS transistor and the bipolar element isolation region. Through these procedures, the epitaxial layer 5 can be made thinner without deteriorating the breakdown strength of N channel type MOS transistor to mount a bipolar transistor operable at very high speed.
申请公布号 JPS62299058(A) 申请公布日期 1987.12.26
申请号 JP19860142073 申请日期 1986.06.18
申请人 MATSUSHITA ELECTRONICS CORP 发明人 SAWADA SHIGEKI
分类号 H01L27/06;H01L21/8249 主分类号 H01L27/06
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