| 摘要 |
PURPOSE:To attain error detection without using a parity bit by retarding a biphase code by 1/2 bit, comparing the retarded biphase code and the original biphase code so as to discriminate the coincidence of the logic level. CONSTITUTION:A clock signal (b) is subjected to 1/2 frequency division by a flip-flop FF2 to obtain a signal (c), which is given to FFs 5, 6. Moreover, the input bihase code is given to a FF 3, retarded by 1/4 bit by using the clock (b), given to a FF 4, where the signal is retarded by 1/4 bit. Then outputs (d), (e) are given to an EOR 7 from the FFs 3, 4. With the outputs (d), (e) coincident, the EOR 7 gives an 'L' output and with the outputs (d), (e) dissident with each other, the EOR 7 gives an 'H' level output to a FF 5. The output of the EOR is always at 'H' at the leading of the signal (c) if no transmission error exists and an output (g) of the FF 5 keeps an 'H' level. If a noise is superimposed as shown in broken lines in figure and part of the signal is changed, since outputs (f), (g) of the EOR 7 goes to 'L' as shown in broken lines in figure, the erroneous bit is detected.
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