| 摘要 |
PURPOSE:To obtain a data processor which accesses a memory at high speed and processes a large amount of data at high speed by computing an address for memory access by an address generating means in parallel to the arithmetic of a computing element. CONSTITUTION:A microprogram instruction outputted by a microcode ROM 2 under the command of a sequencer 1 is synchronized by a pipeline register 3 and outputted to an ALU 4, an address generating circuit 20, and the sequencer 1. While the ALU 4 inputs and outputs data to and from a frame memory 7 according to the microprogram instruction, an address generating circuit 20 computes the address of the frame memory 7 to be accessed next. Consequently, the memory is accessed in a small number of steps and the memory access and the processing of a large amount of data are speeded up. |
