| 摘要 |
PURPOSE:To shorten the occupation time of a high-speed transfer bus and to improve the efficiency of memory access by obtaining a permission for occupation of a low-speed transfer bus and requesting the occupation of the high-speed transfer bus when a memory is accessed by both high-speed and low-speed transfer buses. CONSTITUTION:The processors 3-i-3-m are connected to a memory 1 via a high-speed transfer bus 2 and to processors 5-1-5-1 via a low-speed transfer bus 4 respectively. The memory 1 records exclusive control information. In addition, a high-speed transfer bus occupation request control circuit 7-1 is provided together with a low-speed transfer bus occupation request control circuit 7-2. When the processors 3-i-3-m access the exclusive information on the memory 1, control circuits 6-i-6-m are actuated and the control circuit 6-i, for example, gives a request to the circuit 7-2 for occupation of the bus 4. Then the circuit 6-i gives a request to the circuit 7-1 for occupation of the bus 2 after acquiring the permission for occupation of the bus 4. Thus the exclusive control is attained. |
