发明名称 |
MEASURING INSTRUMENT FOR LOGIC INTEGRATED CIRCUIT |
摘要 |
PURPOSE:To prevent plural DUTs (correcting circuit element to be measured) from malfunctioning owing to wiring capacity by supplying an input signal which is restored accurately by using a latch signal right before the input terminal of a DUT to the input terminal of each DUT. CONSTITUTION:A clock generating device 1 is connected to the input terminal D of s shift register 3 through a frequency divider 2. The output CKphi of the device 1 is supplied to the shift pulse input terminal SP of the register 3 to obtain shift pulses. The register 3 shifts a signal to the terminal D with a signal to the terminal SP and outputs the signal. Output terminals Sphi and S1-Sn are selected with a switch 4 and the signal of the selected terminal is supplied as a latch pulse CKD to CK terminals of FFs Fphi and Fe-Fn. Input signals Aphi and Al-An from a signal source to D terminals of the FFs Fphi and FlnFn are latched with pulses CKD and outputted from output terminals Qo and Ql-Qn as output signals AXphi and Qn. Consequently, the signals which are waveform-shaped right before the input terminals of the DUTs, which are then prevented from malfunctioning. |
申请公布号 |
JPS62297766(A) |
申请公布日期 |
1987.12.24 |
申请号 |
JP19860140689 |
申请日期 |
1986.06.17 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
SOGO YOSHITAKA;USUI SHUNICHI |
分类号 |
G01R31/28;G06F11/22;H01L21/66 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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