Combined circuit switch and packet switching system.

摘要

Apparatus (FIG. 3) for and a method of inserting circuit switch information and packetized data into different time slots of a time division multiplexed bus (320). A memory (l04C) having a location individual to each time slot is written with information specifying whether the time slot individual to each location is to serve circuit switch information or packet data. The readout of each memory location during the occurrence of it's associated time slot controllably effects the application of either the circuit switch information or the packet data to the bus. Packet data can be inserted into each time slot not presently being used by the circuit switch. A special information bit is inserted into each time slot to specify whether the remainder of the bits of the time slot represents circuit switch or packet information. The information bit is used by the receiving apparatus to steer the bits of each time slot to either a receiving circuit switch or a receiving packet switch.