| 摘要 |
PURPOSE:To facilitate the reception processing of a serial data by providing a RAM receiving a data from a serial input terminal to a bit location selected by the output of a shift register and allowing the RAM to send a parallel data to a data bus. CONSTITUTION:With the parallel output of a shift register 100 reaching the value of '00000001', the level of a terminal D of a DFF 400 transits to '1', and the output level of the DFF 400 goes to '1' at the trailing edge of a clock signal fed to a serial clock terminal 10 and an interruption request signal is sent to an interruption output terminal 30. Then the DFF 400 detects it that the output state of the register 100 is circulated to send a reception end signal. As a result, since a microprocessor starts an interruption processing routine, a parallel data is read from the RAM 300 via a data bus 200.
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