发明名称 BUFFER CONTROL CIRCUIT
摘要 PURPOSE:To prevent I/O information for a communication line from being stored in an area where buffer control information is stored and to realize a high reliability memory control by inhibiting a memory access, notifying the occurrence of abnormality and protecting the buffer control information and the I/O information for the communication line if the buffer control information is wrong. CONSTITUTION:An access area normalcy decision circuit 4 decides whether addresses and areas to which three signals, a notification signal 3, a buffer control information area access signal showing that an access to memory made from a local bus 23 targets a buffer control area of an information storage area, and an information storage area access signal are about to access are coincident. If so, a normal operation is made. If not, an access area wrong notification signal 5 notifies the occurrence of abnormality. Simultaneously an access inhibition signal 6 is outputted, and a memory access inhibition circuit 7 inhibits the signals (select 19, Rd 20 and WT 21) of a memory access control circuit from being outputted to a memory.
申请公布号 JPS62296259(A) 申请公布日期 1987.12.23
申请号 JP19860139561 申请日期 1986.06.16
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MASUDA MICHINORI;ONO KENZO
分类号 G06F13/00;G06F12/14;G06F21/24 主分类号 G06F13/00
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