| 摘要 |
PURPOSE:To enable device isolation without increasing the chip area by performing device isolation by a groove and an insulating material filling the groove. CONSTITUTION:Isolation of complementary field effect type transistors is performed by forming a groove 7 between a pair of those transistors and filling it with an insulating material 8. A signal is applied to an input terminal 9, a channel is created between diffusion regions 3 or 6, and an output signal appears at an output terminal 10 in response to the input signal. At this time, even a noise is externally applied to a terminal Vcc, the bi-polar transistors parasitizing the complementary field effect transistors cannot easily form a thyristor due to the device isolation groove 7 and the insulating material 8, so the latch-up phenomenon can be prevented. In this isolation structure, by making its depth deeper than a well 2, device isolation can be done without expanding the chip size. |
