| 摘要 |
PURPOSE:To avoid each processor from waiting for data transfer by allowing each processor to always and exclusively use one out of two or more memories selected according to the same address. CONSTITUTION:In accordance with the states of switching circuits 3 and 5, a master processor 1 is connected to a memory 4 or 6. A slave processor 2 is connected to the memory 6 or 4, whereby each processor can use the memory exclusively without fail. As for data transfer, the master processor 1, for instance, transfers data to the memory 6. Upon the completion of the data transfer, the switching circuit 3 is switched. The master processor 1 transfers data to the memory 6, and the slave processor 2 reads data out of the memory 4. Upon the completion of the data reading, the salve processor 2 switches the switching circuit 5, and reads data in the memory 6. By repeating such actions, data transfer can continue. |
