| 摘要 |
PURPOSE:To reduce the conversion error and to simplify the constitution by sampling and holding the output of a current switch circuit while being controlled by a switching signal synchronously with a clock to cut off a high frequency component. CONSTITUTION:A phase synchronizing oscillation circuit 1 outputs a 4period of switching signal SS in one period of a clock signal CL, DEM current distribution circuits CD1-CD4 are circulated one time at the 4-period of the signal SS and the timewise mean ratio of the currents I0-I7 in one period of the signal CL is 2<0>, 2<1>-2<6>, 2<7>. A current switch 2 connects a current to an output terminal in response to the state of an input data bit to correspond a timewise mean of an analog output A1 at one clock period to the input data. A sample and holding circuit 3 controlled by a signal SS sampled the analog signal A1 in the stable timing to output an analog signal A2. Then an LPF 4 cut off frequency components of the signal A2 in excess of the clock frequency to obtain an analog signal A3.
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