发明名称 BUFFER STORAGE CONTROL SYSTEM
摘要 PURPOSE:To reduce the capacity (in the lateral direction) of storage elements that realize a directory BAA by limiting the number of bits at an absolute address registered in the directory BAA to the number of bits at an accessible address, which are decided by the physical limit of a main storage address MS. CONSTITUTION:All 31 bits apart from the high order three bits are stored at the absolute address in the BAA 107. The output of each row for the column concerned in the BAA 107 is inputted to a comparator 108, and compared with bits corresponding to the absolute address in an address conversion buffer TLB, which are transmitted from a gate 105. The output compared by each comparator 108 is inputted to an encoder 109, and a row in a buffer storage BS 110 registering block data is entry-encoded. Absolute addresses that are slightly below the upper limit of the MS capacity are transferred to a BS. As for any more address, address exception is detected.
申请公布号 JPS62296252(A) 申请公布日期 1987.12.23
申请号 JP19860139663 申请日期 1986.06.16
申请人 HITACHI LTD 发明人 SAKABE TOSHIBUMI;FUKUDA MASAHARU;SAWAMOTO HIDEO
分类号 G06F12/08 主分类号 G06F12/08
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