| 摘要 |
A decoder circuit has a NOR gate (QBo to QBn) arranged to receive address signals (Ao to An), an inverter (Q24) arranged to receive an output of the NOR gate (QBo to QBn), and an output stage arranged to receive outputs of the NOR gate and the inverter and to provide an output signal at either a selected or a non-selected level in dependence upon the address signals.
<??>The load of the NOR gate (QBo to QBn) is a pair (Q21, Q22) of parallel-connected transistors, the gate of one transistor (Q21) being connected to receive a clock signal from a clock signal generating circuit (CG), the gate of the other (Q22) being connected to receive the output signal.
<??>The clock signal generating circuit (CG) generates a clock signal which rises for a preselected period of time in response to appearance of an address signal (Ao). |
