发明名称 SIGNAL PROCESSING CIRCUIT FOR CD PLAYER
摘要 PURPOSE:To attain the access to a RAM without duplication, to eliminate the need for a write priority circuit and to reduce number of components even if jitter takes place in an EFM signal due to an uneven rotation of a disk by providing a delayed flip-flop (D-FF) receiving an AND between an output signal of a flip-flop and a write enable signal. CONSTITUTION:The flip-flop set by a write request signal and the delayed flip-flop receiving an AND between the output signal of the flip-flop and the said write enable signal are provided. Thus, even if the period of generation of a write request signal of a symbol obtained from the EFM signal due to jitter is changed, a write enable signal is generated by a ROM at a period shorter than the generated period. Thus, when the flip-flop is set by the generation of the write request signal, the D-FF is set by the timing of the write enable signal generated before the next write request signal is produced and the write signal is generated.
申请公布号 JPS62295267(A) 申请公布日期 1987.12.22
申请号 JP19860115097 申请日期 1986.05.20
申请人 SANYO ELECTRIC CO LTD 发明人 OZAWA TOSHIYUKI;HOSHI TERUO;NAGASAWA TAKAFUMI;KIMURA KAZUHIRO;ARAI HIROYUKI
分类号 G11B20/10;G11B20/18 主分类号 G11B20/10
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