| 摘要 |
PURPOSE:To attain a high speed circuit without being affected by the data length to be multiplied by splitting an input data at each bit and applying the parallel processing by the multiplication between the data of one bit having each weight and a filter coefficient data thereby converting the operation processing into a switching operation. CONSTITUTION:ROM circuits 111-114 store five kinds of filter coefficient data corresponding to the order of filter and the data are weighted correspond ing to the rank of each bit. The operation of multipliers 181-184 is the multipli cation of filter coefficient data of one bit to prescribed bit. Thus, the multipliers 181-184 are constituted by a multi-array switch. That is, when a data from leads L0-L4 is logical '1', the filter coefficient data from coefficient data setting sections 161-165 is led to adders 191, 194, and when logical '0' all the outputs by dat bit number are brought into logical '0'. The processing time of the switching operation as above is much reduced in comparison with the multiplication of digital signals.
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