| 摘要 |
PURPOSE:To improve a reliability adding a memory cell of about two times and one sense amplifier for a parity bit. CONSTITUTION:The contents of an address designated by an address decoder 2 are read through a reading/writing buffer 3 from a non-volatile memory 1 and the contents of the reading/writing buffer 3 are written in the address designated by the address decoder 2. The address decoder 2 is constituted so as to select two memory addresses by one address signal. The two bytes of the non-volatile memory 1 is read in time division to make apparently equal to the reading of one byte. The parity check is carried out in a parity generating circuit 4, when the same parity signal as one at the time of writing is detected, a clock is outputted from an AND circuit 5 and the output of the non-volatile memory 1 is inputted to the reading/writing buffer 3.
|
