发明名称 MEMORY SHARED CONTROLLING CIRCUIT
摘要 PURPOSE:To prevent an access competition, and also, to reduce an overhead of a processor by constituting the circuit so that an access by one of two sets of processors is allowed, whenever the other, processor ends an access of one cycle. CONSTITUTION:Two processors are supplied to a memory shared controlling circuit 3 through the respective buses, and the controlling circuit concerned 3 is provided with gate switches 31, 32 for coupling each bus of control, address and data between a memory 4 and the processors 1, 2. When one processor starts write or read-out, the other processor is brought to a pause, and when it is ended, flip-flops 37, 38 are reset, and also, the processor itself is brought to a pause by the time which is set to monostable multivibrators 315, 316, and when a control signal of the other processor is generated during that time, the pause is continued.
申请公布号 JPS62293458(A) 申请公布日期 1987.12.21
申请号 JP19860136996 申请日期 1986.06.12
申请人 MEIDENSHA ELECTRIC MFG CO LTD 发明人 TAKEGAWA EIZO
分类号 G06F15/16;G06F9/52;G06F15/177;G11C8/16 主分类号 G06F15/16
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