| 摘要 |
PURPOSE:To reduce a burden of a software, and to execute a memory access at a high speed by giving a priority to chip selecting signals which are generated by plural processors. CONSTITUTION:When a processor 1 generates an address of a shared memory 7, a decoder 10 decodes this address, and generates a chip selecting signal (a). As a result, a controlling circuit 9 generates an inhibiting signal (h), inputs it to a gate circuit 5 and 6, and detaches an address bus 12 and a data bus 13 from a processor 2. In case when the processor 1 and 2 generate the address of the shared memory 7 at the same time, and the chip selecting signal (a) and (b) have been inputted to the controlling circuit 9 at the same time, the controlling circuit 9 makes the priority which has been allocated to the processor, and detaches other processor from the bus. |
