| 摘要 |
PURPOSE:To prevent mis-write and to apply diagnosis at the time of fault generation by providing a parity check circuit for input/output data. CONSTITUTION:A static RAM array SRAM is provided with an input/output data parity check circuit PC and the parity check of input data D0-D7 written in memory arrays M-ARY0-M-ARYP is applied via a data input buffer DIB from a CPU. If an error exists in the data D0-D7, the circuit PC controls a buffer DIB and no write in the memory array is applied. Further, the output data via an output buffer DOB from the memory arrays M-ARY0-M-ARYP is subjected to parity check by the circuit PC and the transmission to the CPU is controlled. Thus, diagnostic processing at the time of fault generation is applied easily and properly and mis-write in the memory arrays is prevented.
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