| 摘要 |
PURPOSE:To reduce the hardware quantity of an instruction decoder by always having adjacent instruction codes on an instruction map where higher and lower bits are arranged in order of gray codes to the vertical and horizontal axes of each instruction code. CONSTITUTION:On an instruction map of an instruction decoder, the higher four bits I7, I6, I5 and I4 of an instruction code are arranged to a vertical axis in order to gray codes together with the lower four bits I3, I2, I1 and I0 are arranged to a horizontal axis also in order of gray codes respectively. In such a way, the binary expression alpha000100X1 (X: pi length bit) is available in an area 11 set at the same position of a conventional area 21 in terms of an instruction code of a single type together with the binary expression 'X1000100' available in an area 12 set at the same position as a conventional area 22 respectively. Thus it is possible to obtain an instruction decoder circuit with which the types of output signals are decreased. |
