发明名称 DECIMAL ADDITION/SUBTRACTION SYSTEM
摘要 PURPOSE:To perform a decimal multiple operation with the same instruction regardless of an operator by using a register to store the designated operator and carrying out successively the operations divided by an arithmetic instruction common with the flag of said register. CONSTITUTION:The instruction code part of an arithmetic instruction M is decoded by a decoder 11 and erases the flag of a flag register 12 via an inverter 13 and an OR circuit 14 to set it at 0 when a processing instruction ABCD instructing the addition of decimals including no positive/negative code is outputted in the form of value '1'. While a flag 1 is set to the register 12 via the circuit 14 when a processing instruction SBCD instructing the subtraction of decimals including no positive/negative code is outputted in the form of '1'. In such a way, a decimal arithmetic circuit carries out successively additions or subtractions in response to the flag state of the register 12 after an arithmetic instruction DCE is received.
申请公布号 JPS62293342(A) 申请公布日期 1987.12.19
申请号 JP19860134938 申请日期 1986.06.12
申请人 FUJITSU LTD 发明人 TORII KOJI;KITAHARA TAKESHI
分类号 G06F7/494;G06F7/50 主分类号 G06F7/494
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