发明名称 INTERFACE SYSTEM BETWEEN COMPARATOR AND LOGIC CIRCUIT
摘要 PURPOSE:To suppress the increase of power consumption, by providing a gate circuit which controls the output of a comparator between the comparator having the cancel function of an offset voltage, and a MOS logic circuit. CONSTITUTION:A comparator 6 is constituted of switched capacitors 1-4, and an operational amplifier, and has the cancel function of an offset voltage VOFF. A NOR gate 23 is provided between the output 9 of the circuit 6, and a CMOS logic circuit 13. The terminal 26 of the gate 23 is controlled at a level '0' at the time of performing no offset cancel function by the circuit 6. Thereby, the inversion level of the output 9 of the circuit 6 is outputted to the output terminal 25 of the gate 23, and it is inputted as it is to the circuit 13. Since a transistor Tr15 is turned off by controlling the terminal 26 at a level '1' while executing the offset cancel function, no through current is permitted to flow through the circuit 23 itself, and a Tr18 is energized, then the terminal 25 is set at the level '0l compulsorily. Therefore, no through current is permitted to flow from the circuit 6 to the circuit 13 by the action of the circuit 23, thereby, it is possible to reduce the power consumption.
申请公布号 JPS62292013(A) 申请公布日期 1987.12.18
申请号 JP19860136685 申请日期 1986.06.11
申请人 NEC CORP 发明人 ICHIHARA MASAKI
分类号 H03K19/0185;H03F3/34;H03K3/02;H03K5/08;H03K19/00 主分类号 H03K19/0185
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