| 摘要 |
PURPOSE:To realize a logarithmic amplifier in a MOS integrated circuit, and to reduce a consumption current, by connecting in common each in-phase output of all of the two pairs of differential pairs in a cascade-connected multistage MOS type differential amplifier. CONSTITUTION:The ration W/L of the gate widths W to the gate lengths L of MOS type differential pair of transistors TRT01 driven by current sources I01, I02,...I0n, are set in equal, and the drains of the TRs are connected in common, and the outputs are sequentially cascade-connected. A square full-wave rectifier is formed by setting the W/L of two pairs of MOS type differential pair of TRs T11 and T1k driven by each two of current sources I01, I02,...In, and In+1, as 1/k(k>1), and setting the outputs adversely with each other. Each in-phase output of the two pairs of differential pairs is connected in common. As for the outputs V1-VOUT of the differential pair T01, etc., the outputs from the VOUT to the VIN are saturated sequentially, as increasing an input signal VIN. Therefore, an output current IOUT becomes the sum of a differential current I1=(I1-I2)-(I4-I3), etc., at each stage, by the TRs T10-T60, and a proximate logarithmic characteristic to the signal VIN is given to the IOUT. |
