| 摘要 |
PURPOSE:To reduce memory capacity, by a method wherein the first stage FF of the shift register of a scan-pass circuit is constituted so as to be provided with set and reset terminals and both terminals are used as the input terminals of a test signal and the output and input terminals of the final and first stage FFs are connected. CONSTITUTION:FFF1-Fj internally present constitute a shift register 1 and first stage FFF1 has set and reset terminals S, R and the scan-pass test signal SI1, SI2 from a test pattern memory circuit 2 are respectively inputted to the terminals S, R. The output terminal of final stage FFFj outputs a scan-out signal SO and is connected to the input terminal of FFF1 to constitute a scan- pass circuit. Herein, a value set to all of FFs with respect to a first test and the values of the input number of times of clock pulse CK replacing the value of FF of a stage to be replaced and after a second test and information showing whether the value at that time is set to '1' or '0' may be stored in the memory of the circuit 2 corresponding to FF to be altered. |
