发明名称 DIGITAL CONVERGENCE CORRECTION CIRCUIT
摘要 PURPOSE:To perform excellent convergence correction, by rearranging a correction data at a representative point stored in a memory at the time of switching a deflection frequency, at the same position on a picture plane, and keeping the amplitude of an interpolation factor signal in constant invariably regardless the deflection frequency. CONSTITUTION:The correction data at a certain representative point is inputted from a memory 3 in which a correcting quantity at the representative point is stored, to the binary input of an MDAC(multiplition type DA conversion)5, and the correction data at the representative point of low-order stage by one, are inputted simultaneously to the binary input of a MDAC6. Memory addresses to read out those correction data are supplied by a horizontal address counter 1, and a vertical address counter 2. A binary output from the vertical address counter 2 is added on an interpolation factor circuit 4, and from the interpolation factor circuit 4, interpolation factors K, and 1-K are outputted, and they are added on the MDACs 5 and 6, respectively. The outputs of the MDACs 5 and 6, after being synthesized at an adder 7, are outputted as correction waveforms through an LPF8.
申请公布号 JPS62291283(A) 申请公布日期 1987.12.18
申请号 JP19860133823 申请日期 1986.06.11
申请人 HITACHI LTD 发明人 FUNADA ETSUO;OSAWA MICHITAKA
分类号 H04N9/28 主分类号 H04N9/28
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