| 摘要 |
PURPOSE:To control the relation in order between the address signals and output data, and to make the titled memory usable for plural uses by adding a semiconductor memory with a data line switching signal line and a data line switching circuit to change over the connection between a data line and a data output terminal. CONSTITUTION:In case '1' is added to a data line switching signal H/V, line decoders R3-R5 newly added do not turn to be active. In case '00' is inputted respectively to line addresses CA0, CA1, and line addresses RA0 and RA1, address decoders A0 and R0 turn to be active. And the contents of memory cells C000-C200, C010-C210, and C020-C220 are outputted to respective data lines D00-D20, D01-D21, D02-D22, transfer gates T00-T02 are electrified, and finally the contents of the memory cells C000, C010, and C020 are outputted to respective data output terminals DB0, DB1, and DB2. Next, in case '0 is inputted for a data line switching signal H/V, the address decoders R0-R2 do not turn active, but either one of R3-R5 turns active in accordance with line address signals RA0, RA1.
|
