| 摘要 |
Disclosed is an electrically alterable, floating gate type, nonvolatile, semiconductor memory device wherein the gate oxide layer (9') in the "injection" area between the silicon (17) (drain region of the device) and the floating gate (19), has an increased thickness in respect of the thickness of the same gate oxide layer (14) over the channel region (15) of the device in order to decrease the parasitic capacitance of the injection area, thus improving the programming threshold voltage characteristics. A method for fabricating the improved memory device is also disclosed. |
