发明名称 TELEVISION RECEIVER
摘要 PURPOSE:To eliminate possibility of giving incorrect recognition, by erasing a video signal at the time of selecting a channel, simultaneously interrupting the supplying of a clock to an on-screen displaying character generator, and erasing an on-screen displaying output. CONSTITUTION:On the base side of a transistor TR1, a mute pulse M generated at a channel selecting time is impressed through a resistor R1. Also, on the collector side of the transistor TRm, a clock signal C required for the outputting the output of a character generator circuit 3, is impressed. At the time of selecting the channel, the mute pulse N is impressed on the base of the transistor TR1 from a channel selection circuit 1 through the resistor R1, and the transistor TRm is turned 'ON' only at the time of switching the channel, and the clock signal C is dispersed to the earth. Therefore, no on-screen output signal is outputted. Simultaneously, a video signal is controlled by a video defeat circuit 6, thereby, the video signal is also erased.
申请公布号 JPS62290280(A) 申请公布日期 1987.12.17
申请号 JP19860134136 申请日期 1986.06.10
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 AKIYOSHI TAKESHI
分类号 H04N5/445 主分类号 H04N5/445
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