| 摘要 |
<p>A programmable logic array (10) employing arrays (15 and 27) of electrically erasable and programmable cells. The programmable logic array (10) includes a dual purpose programming circuit (21 and 31) which is employed to provide programming data to an AND array (15) to program the AND array cells, and to provide OR array row selection data during OR array programming, thereby eliminating the need for a separate OR array row decoder. A method and apparatus is also disclosed for efficiently testing the AND array cells (15) and input circuitry (11) by bulk stripe programming the array cells.</p> |
