| 摘要 |
PURPOSE:To obtain a three-state circuit requiring only a small area byy serially connecting a transfer gate consisting of N or P channel type MOS transistors to gates in MOS transistors comprising a CMOS output circuit and further connecting the gates to a positive potential and a ground. CONSTITUTION:When a high level signal is impressed on an enable signal input terminal 18, NMOSs 11 and 12 are turned on. An inverter 10 inverts a data signal impressed on a data signal input terminal 17, and low level signals are impressed on gates in a PMOS 13 and an NMOS 14. The high level signal shows up in an output terminal 19. Whereas the impressed data signal is at a low level, the signal at a low level appears in the output terminal 19. When the low level signal is impressed on the enable signal input terminal 18, the NMOSs 11 and 12 turned off. The PMOS 13 and the NMOS 14 are off together, and the output terminal 19 attains a high impedance state. |
