| 摘要 |
PURPOSE:To improve an operation margin by providing a transistor TR which is controlled with an address latch signal as the gate input. CONSTITUTION:An external address input AIN is subjected to signal amplification by a latch consisting of multistage inverter circuits. A TR Q7 which is controlled with an address latch signal phiA, which is a one shot signal taking charge of address latch operation, as the gate input is provided between the latch 1 and a TR Q4 which is controlled with an inverter output N1 of the preceding stage as the gate input and pulls down the inverter output of a second stage to an earth potential. Thus, information in a level VDD can be supplied even if the signal phiA is not sufficiently raised to the level VDD in the input of the inverter circuit of a third stage, and the level dependency of the signal phiA is reduced.
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