发明名称 GENERATING SYSTEM FOR CONDITIONAL CODE IN DECIMAL OPERATION
摘要 PURPOSE:To facilitate generating programs and use an operation instruction which does not directly designate addition/subtraction, by using four generated condition codes for inversion of the sign of the operation result of a decimal operation circuit and conversion to a complement and using them for decision of a branch condition similarly to a binary. CONSTITUTION:The first and second numerical values A and B and respective signs are stored in registers 111 and 112 of a system and the are operated by a decimal operation circuit 12. If carry or borrow is generated as the operation result of the circuit 12, the first condition code C is outputted from an OR circuit 13. Signs of numerical values in registers 111 and 112 are checked by a sign checking circuit 14 to input '0' for positive and '1' for negative to an AND circuit 15, and the second condition code N is outputted from this circuit 15. Condition codes Z And V are outputted from an inverter 17 and an OR circuit 20 respectively. A logic similar to that for binaries is used for decision of branch condition, and generation of the operation program of the circuit 12 is facilitated.
申请公布号 JPS62288936(A) 申请公布日期 1987.12.15
申请号 JP19860131709 申请日期 1986.06.09
申请人 FUJITSU LTD 发明人 TORII KOJI;KITAHARA TAKESHI
分类号 G06F7/50;G06F7/494;G06F7/508 主分类号 G06F7/50
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