发明名称 WAVEFORM MEMORY APPARATUS
摘要 PURPOSE:To simplify circuit constitution by reducing the number of pre-trigger counters, by constituting a pre-trigger circuit using an address generator for making a trigger enable signal active and a presettable counter. CONSTITUTION:An address generator AG has function capable of setting a start address ast, and the sample timing signal clk from a timing control circuit TMC and the stop signal stp obtained from a presettable counter PC2 are applied to said address generator AG and address output is applied to the address terminal ADR of a memory RAM. The address generator AG makes a trigger enable signal ten active when an address value becomes max. and returns to zero and said signal ten is applied to a trigger control circuit TC. By this mechanism, a waveform memory apparatus wherein the constitution of a pre-trigger circuit is simplified can be obtained.
申请公布号 JPS62288580(A) 申请公布日期 1987.12.15
申请号 JP19860131454 申请日期 1986.06.06
申请人 YOKOGAWA ELECTRIC CORP 发明人 NAKAJO KOICHI
分类号 G01R13/20;G11C27/00 主分类号 G01R13/20
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