<p>A high speed data storage array is defined utilizing a unique cell design for high speed sampling of a rapidly changing signal. Each cell of the array includes two input gates between the signal input and a storage capacitor. The gates are controlled by a high speed row clock and low speed column clock so that the instantaneous analog value of the signal is only sampled and stored by each cell on coincidence of the two clocks.</p>
申请公布号
CA1230421(A)
申请公布日期
1987.12.15
申请号
CA19850478018
申请日期
1985.04.01
申请人
BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UNIVERSITY (THE)
发明人
WALKER, JAMES T.;LARSEN, RAYMOND S.;SHAPIRO, STEPHEN L.;CHAE, SOO I.;FREYTAG, DIETRICH R.;BREIDENBACH, MARTIN