| 摘要 |
PURPOSE:To generate all states in parallel outputs internally with a few clock pulses by connecting a selector to a data input and a clock input of a D flip-flop and constituting the counter circuit by a switching input. CONSTITUTION:Captions 11a-11d and 12a-12g show D flip-flops and sectors respectively. In selecting a switching input as logical L, the same circuit as a conventional serial conversion circuit is obtained. In selecting the switching input as logical H, a Q output is given to a data input by the selectors 12a-12g and the Q output of the pre-stage is given to the clock input of the 2nd and succeeding stages. That is, the circuit acts like a 4-bit ripple carry binary counter and parallel outputs Q1-Q4 change its state sequentially every time one clock pulse is inputted, and all states of the combination of aparallel outputs is generated by inputting 16 (=2<4>) clock pulses. |
