| 摘要 |
The invention relates to a system for testing the failure or satisfactory operation of a logic component circuit. The system comprises a generator, whose outputs are respectively connected to the simulation inputs of the components, in order to apply thereto simulation signals having a first or a second logic state, as well as testing means connected to the output of the circuit and able to mark the logic level of the output signal of said circuit. The testing means comprise a counter having an input for loading a predetermined value corresponding to the number of components to be simulated in the testing circuit, as well as another counter connected to the outputs of the generator for receiving a resetting signal and incrementation pulses. These means also comprise means for marking the logic level of the output signal of the circuit. Application to the testing of circuits having logic components.
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