| 摘要 |
A method of manufacturing a semiconductor device wherein the proportion of the area occupied by the source and drain regions can be reduced. In this method, the side walls of a gate electrode are first selectively deposited with an insulating film, then conductive material layers are selectively formed on the source and drain regions, partially extending to side portions of an element isolation regions, and, after forming an insulating protective film over the entire surface of the resultant structure, contact holes are formed to reach the conductive material layers for forming source and drain wiring layers.
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