发明名称 MULTI CPU SYSTEM
摘要 PURPOSE:To attain an effective synchronization between CPU systems and to reduce the load of a software by reading transmission data by a remote side, thereafter returning to a transmission source, writing in a return receiving memory and reading it by the transmission source. CONSTITUTION:A writing/reading control part 5 actually writes the data to a writing memory 6 to the writing of information from a CPU system 11 and the system 11 reads the data from the return receiving memory 14 at the time of reading the data. Herein, the data of the memory 6 is read in a transmission part 7, transmitted to the receiving part 8 of the CPU system 12 periodically, received and written in the memory 9. When the system 12 reads the information through a reading control part 10, it is written in a return transmission memory 11. This information is read in a return transmission part 12, fed to the system 11 in the timing of a communication and received in a return receiving part 13 and written in a return memory 14. As a result, when the system 11 reads the information of the memory 14 through the control part 5, the contents are the same contents read by the system 11 to synchronize an information interchange.
申请公布号 JPS62286156(A) 申请公布日期 1987.12.12
申请号 JP19860129294 申请日期 1986.06.05
申请人 YASKAWA ELECTRIC MFG CO LTD 发明人 SHIBATA MOTONOBU
分类号 G06F15/16;G06F15/177 主分类号 G06F15/16
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