| 摘要 |
<p>PURPOSE:To reduce jitter in an output timing pulse by applying an input timing pulse to o leading or trailing detection means so as to extract a timing pulse synchronously with a self-traveling internal clock and coincident with the period of the input timing pulse. CONSTITUTION:A leading detector 8' outputs a timing pulse synchronously with an input timing pulse and a self-running internal clock and coincident with the period of the input timing pulse. The timing pulse is added as an enable signal and the self-traveling internal clock is applied as a clock to a counter 93, the load priority is obtained with a switching signal at level '1', and the count state is attained with the switching signal at '0'. Then a selector 6 acts like to output the input timing pulse with the switching signal at level '1' and the output timing pulse with a period being e.g., ten times of the period of the input timing pulse with the switching signal at/'0'. Thus, the jitter of the output timing pulse is reduced.</p> |
